1. Field of the Invention
The present invention relates to a wafer-scale integrated circuit wherein a plurality of integrated circuit cells are fabricated on a semiconductor wafer, together with a port for external coupling thereto, a first of said cells being accessible from said port and operable to establish functional coupling to a neighboring cell, the neighboring cell being similarly operable to establish functional coupling to another neighboring cell, and so on, until a serpentine chain of functionally intercoupled cells is provided on the wafer.
2. The Prior Art
It is known to provide an integrated circuit, suitable for fabrication over the entire surface of a semi-conducter wafer upwards of 6 cm in diameter, wherein the inherent failure rate for fabrication of such a large circuit is overcome by providing that the circuit comprises a plurality of substantially independent cells which may be independently tested and incorporated into the overall working of the circuit if found to be functional, non-functional cells being excluded from the circuit. It is generally the case that starting at a coupling port, provided on the wafer for external coupling thereto, a first cell in its vicinity is coupled to and tested. If the first cell works to an acceptable standard, the first cell is commanded to couple to a second, neighboring cell and it too is tested. If the second cell fails the test another neighbor is selected for testing. If the second cell passes the test it is commanded to couple to a third cell so that it too may be tested, the third cell thereafter coupling to a fourth cell, and so on until a serpentine chain of tested, acceptably functional intercoupled cells is formed on the surface of the wafer. When the chain comprises sufficient elements, its growth is terminated and the chain used as a data processing element.
It is also known that such cells in a wafer-scale circuit comprise coupling elements for coupling to neighboring cells, supervisory elements for control within each cell, and data processing elements for performing the data processing functions which are the purpose for the existence of that cell. In the prior art it has been a requirement that, in order to pass the functional test, a cell has had to be entirely functional, failure of any part of its various elements being sufficient to exclude that cell from any kind of use.
In the growth of a chain of intercoupled cells on a wafer, it is often the case that the tip of the chain becomes boxed in by surrounding cells which do not pass the functional test and therefore inhibit further growth. In the worst case whole areas of the wafer may be excluded from access from the coupling port by being surrounded by cells which fail testing.
In the particular case of such cells being used for data storage, that is, as an integrated circuit memory, it is usual that the internal configuration of each cell consists of one or more shift registers coupled in series. If any one element of any one of the shift registers fails, the entire cell is useless. In addition, the constant movement of data within the shift register or registers, and as is commonly the case, between the adjacent cells, makes keeping track of the location of data records and access thereto extremely difficult.
It is therefore desirable to provide such a cell which is tolerant of at least partial failure of the elements therein. It is also desirable to provide a cell which will not inhibit growth despite partial or total loss of data processing capacity, thereby allowing access to other cells where said capacity may be obtained. It is yet further desirable to provide a cell, for data storage, wherein the location of data records is fixed.